1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device which can operate selectively in a plurality of operation modes, and has a structure which can achieve a low current consumption and a fast operation.
2. Description of the Background Art
A semiconductor memory device in the prior art will be briefly described below with reference to FIG. 11.
A semiconductor memory device 9000 in the prior art shown in FIG. 11 includes input buffers 1.1, 1.2, . . . , 1.m, an internal circuit 900 and output buffers 9.1, 9.2, . . . , 9.n.
Input buffers 1.1, 1.2, . . . , 1.m, which will be generally referred to as "input buffers 1" hereinafter, determine logical levels of externally applied signals EXT1, EXT2, . . . , EXTm, and thereby produce internal signals at the corresponding logical levels for sending them to internal circuit 900, respectively. Internal circuit 900 performs predetermined operations in accordance with internal signals sent from input buffers 1, respectively. Output buffers 9.1, 9.2, . . . , 9.n amplify signals produced by internal circuit 900 and externally output them (signals D1, D2, . . . , Dn). Input buffer 1 may be an LVTTL interface which is a typical example of a TTL (Transistor Transistor Logic) interface.
An example of a specific structure of input buffer 1 will be described below with reference to FIG. 12.
Input buffer 1 shown in FIG. 12 is a kind of an NOR circuit, which is a kind of conventional LVTTL interface, and will be simply referred to as an NOR circuit 1.
NOR circuit 1 shown in FIG. 12 includes P-channel MOS transistors PLT1 and PLT2 as well as N-channel MOS transistors NLT1 and NLT2. P-channel MOS transistors PLT1 and PLT2 are connected in series between a power supply potential VDD and one of conductive terminals of each of N-channel MOS transistors NLT1 and NLT2. The other conductive terminal of each of N-channel MOS transistors NLT1 and NLT2 is connected to the ground potential.
A gate electrode of each of P-channel MOS transistor PLT2 and N-channel MOS transistor NLT1 receives an input signal VIN (one of signals EXT1, EXT2, . . . , EXTm in FIG. 11).
P-channel MOS transistor PLT2 and N-channel MOS transistor NLT1 form a CMOS inverter. P-channel MOS transistor PLT1 and N-channel MOS transistor NLT2 are control transistors each receiving on the gate electrode an active signal SEL. NOR circuit 1 is enabled and disabled in response to turn-on and turn-off of P-channel MOS transistor PLT1 and N-channel MOS transistor NLT2.
Signal VOUT is issued from the connection node of P-channel MOS transistor PLT2 with respect to N-channel MOS transistors NLT1 and NLT2 in response to input signal VIN. Signal VOUT is sent to internal circuit 900 shown in FIG. 11.
In the case of the LVTTL interface, the upper and lower limits of the potential of externally supplied input signal VIN are 2.0 V and 0.8 V (LVTTL level), respectively.
At the LVTTL level, all the MOS transistors forming interface circuit 1 are turned on so that a through current flows. In view of this, interface circuit 1 is constructed to be deactivated (disabled) in response to activating signal SEL for preventing wasteful consumption of power at the interface portion when the chip is unselected.
An operation of NOR circuit 1 shown in FIG. 12 will be described below. When activating signal SEL is at the L-level and therefore inactive, P-channel MOS transistor PLT1 is turned on, and N-channel MOS transistor NLT2 is turned off. This enables the input of input signal VIN. For example, when input signal VIN at H-level (2.0 V) is applied, N-channel MOS transistor NLT1 is turned on to output signal VOUT at L-level. When input signal VIN (0.8 V) at L-level is input, P-channel MOS transistor PLT2 is turned on to output VOUT at H-level.
When activating signal SEL is at H-level and therefore inactive, P-channel MOS transistor PLT1 is turned off, and N-channel MOS transistor NLT2 is turned on. Thereby, NOR circuit 2 is disabled, and output signal VOUT is fixed at L-level independently of input signal VIN.
The LVTTL interface meets specifications for power supply voltage VDD of 3.3V, and can cover the operation frequency in a range from about 60 MHz to about 100 MHz.
The operation frequencies of CPUs, MPUs and others have recently increased, and the demand for speeding up the logical interfaces coupled to these memories has further increased.
Under the above situation, the LVTTL interface has reached the limit. In the structure using the TTL interface, no problem arises if the operation frequency is low. If the operation frequency is high, however, overshoot and undershoot become remarkable. Also, serious problems arise in the operation of the whole chip because noises, which are caused by variation in power supply potential and ground potential due to switching, as well as reflection noises and other noises such as cross-talk noises increase. The bus system suffers from such a problem that the power consumption of the device increases due to a large amplitude (i.e., a width of an LVTTL level) of the signal transferred thereby. Therefore, it is necessary to provide a practically available fast interface which can reduce the amplitude of the signal.
As one of the measures, there is an SSTL (Stub Series Terminated Logic) which is a fast interface. A structure of the SSTL interface will be described below with reference to FIG. 13.
As shown in FIG. 13, SSTL interface circuit 2 includes P-channel MOS transistors PST1 and PST2 as well as N-channel MOS transistors NST1, NST2 and NST3. SSTL interface circuit 2 is formed of a differential amplifier circuit. In the following description, SSTL interface circuit 2 is called simply as a differential amplifier 2.
As shown in FIG. 13, P-channel MOS transistor PST1 and N-channel MOS transistor NST1 are connected in series between power supply node VDD and a node Z1. P-channel MOS transistor PST2 and N-channel MOS transistor NST2 are connected in series between power supply node VDD and node Z1.
Both the gate electrodes of P-channel MOS transistors PST1 and PST2 are connected to a connection node (represented as a node X1) between P- and N-channel MOS transistors PST1 and NST1.
The gate electrode of N-channel MOS transistor NST1 receives reference potential Vref which is an intermediate potential equal to, e.g., ((power supply potential VDD).times.0.45) and therefore equal to about 1.5 V if power supply potential VDD is 3.3 V. N-channel MOS transistor NST2 receives input signal VIN on its gate electrode. Input signal VIN is a signal which oscillates with a small amplitude VH of, e.g., .+-.0.4 V with respect to reference voltage Vref.
N-channel MOS transistor NST3 is connected between node Z1 and the ground potential. N-channel MOS transistor NST3 receives activating signal SEL on its gate electrode. N-channel MOS transistor NST3 is a control transistor, and differential amplifier 2 is enabled/disabled in response to turn-on/off of N-channel MOS transistor NST3.
Signal VOUT is output in response to input signal VIN from the connection node between P-channel MOS transistor PST2 and N-channel MOS transistor NST2. Signal VOUT is transferred to internal circuit 900 shown in FIG. 11.
Then, an operation of differential amplifier 2 shown in FIG. 13 will be described below. When activating signal SEL is at L-level and therefore active, differential amplifier 2 is enabled to amplify and output the potential difference between input signal VIN and reference voltage Vref. For example, when input signal VIN at H-level is supplied, signal VOUT falls to L-level. When input signal VIN at L-level is supplied, signal VOUT rises to H-level.
When activating signal SEL is at H-level and therefore inactive, differential amplifier 2 is disabled, and output signal VOUT is fixed at L-level independently of input signal VIN.
The structure of differential amplifier 2 has an electrically parallel twisted pair line structure so that noise components cancel each other. This allows fast transmission of signals of a small amplitude.
Differential amplifier 2 shown in FIG. 13 is always supplied with reference voltage Vref which is an intermediate potential so that N-channel MOS transistor NST1 is always on.
Therefore, node X1 is pulled toward the ground potential when activating signal SEL is at H-level and therefore is enabled. When the potential on node X1 exceeds the threshold voltage of P-channel MOS transistor due to the foregoing, P-channel MOS transistor PST1 starts to be turned on so that the potential on node X1 will be fixed at the potential which keeps a balance in power or performance between the current supplied from P-channel MOS transistor PST1 and the current supplied from N-channel MOS transistor NST1.
This means that a through current (current) flows from P-channel MOS transistor PST1 through N-channel MOS transistor NST1 when activating signal SEL is at H-level (enabled).
Accordingly, semiconductor memory device 900 employing differential amplifier 2 shown in FIG. 13 suffers from such a problem that a large through current (consumed current) flows as long as it accepts the input signal even if it is desired to minimize the power consumption in the currently selected operation mode.